文献
J-GLOBAL ID:201702257805206319
整理番号:17A1571299
修正加算器を用いた提案された高速64ビットVLIWマイクロプロセッサ【Powered by NICT】
Proposed high speed 64-bit VLIW microprocessor with modified adders
著者 (5件):
Jain Karan
(Department of Electronics and Communication Engineering, Amity School of Engineering and Technology, Noida)
,
Verma Aishwarya
(Department of Electronics and Communication Engineering, Amity School of Engineering and Technology, Noida)
,
Tyagi Devyani
(Department of Electronics and Communication Engineering, Amity School of Engineering and Technology, Noida)
,
Mehra Anu
(Department of Electronics and Communication Engineering, Amity School of Engineering and Technology, Noida)
,
Gaur Nidhi
(Amity University Uttar Pradesh, India)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
SPIN
ページ:
316-319
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)