文献
J-GLOBAL ID:201702262813417472
整理番号:17A0605037
DRAM積層した1/2.3インチ20Mピクセル3層構造のCMOSイメージセンサ
A 1/2.3in 20Mpixel 3-Layer Stacked CMOS Image Sensor with DRAM
著者 (20件):
HARUTA Tsutomu
(Sony Semiconductor Solutions, Atsugi, JPN)
,
NAKAJIMA Tsutomu
(Sony Semiconductor Solutions, Atsugi, JPN)
,
HASHIZUME Jun
(Sony Semiconductor Solutions, Atsugi, JPN)
,
UMEBAYASHI Taku
(Sony Semiconductor Solutions, Atsugi, JPN)
,
TAKAHASHI Hiroshi
(Sony Semiconductor Solutions, Atsugi, JPN)
,
TANIGUCHI Kazuo
(Sony Semiconductor Solutions, Atsugi, JPN)
,
KURODA Masami
(Sony Semiconductor Solutions, Atsugi, JPN)
,
SUMIHIRO Hiroshi
(Sony Semiconductor Solutions, Atsugi, JPN)
,
ENOKI Koji
(Sony Semiconductor Solutions, Atsugi, JPN)
,
YAMASAKI Takatsugu
(Sony Semiconductor Manufacturing, Atsugi, JPN)
,
IKEZAWA Katsuya
(Sony Semiconductor Solutions, Atsugi, JPN)
,
KITAHARA Atsushi
(Sony Semiconductor Solutions, Atsugi, JPN)
,
ZEN Masao
(Sony Semiconductor Solutions, Atsugi, JPN)
,
OYAMA Masafumi
(Sony Semiconductor Solutions, Atsugi, JPN)
,
KOGA Hiroki
(Sony Semiconductor Solutions, Atsugi, JPN)
,
TSUGAWA Hidenobu
(Sony Semiconductor Solutions, Atsugi, JPN)
,
OGITA Tomoharu
(Sony Semiconductor Solutions, Atsugi, JPN)
,
NAGANO Takashi
(Sony Semiconductor Solutions, Atsugi, JPN)
,
TAKANO Satoshi
(Sony LSI Design, Atsugi, JPN)
,
NOMOTO Tetsuo
(Sony Semiconductor Solutions, Atsugi, JPN)
資料名:
電子情報通信学会技術研究報告
(IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
巻:
117
号:
9(ICD2017 1-18)
ページ:
95-98
発行年:
2017年04月13日
JST資料番号:
S0532B
ISSN:
0913-5685
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
日本 (JPN)
言語:
英語 (EN)