文献
J-GLOBAL ID:201702265628417365
整理番号:17A1727267
動的MOSFETの劣化とその検証に基づく回路加齢モデル化【Powered by NICT】
Circuit-aging modeling based on dynamic MOSFET degradation and its verification
著者 (9件):
Rohbani Nezam
(Department of Computer Engineering, Sharif University of Technology, Tehran, Iran)
,
Miyamoto Hidenori
(HiSIM Research Center, Hiroshima University, Higashi-Hiroshima 739-8530, Japan)
,
Kikuchihara Hideyuki
(HiSIM Research Center, Hiroshima University, Higashi-Hiroshima 739-8530, Japan)
,
Navarro Dondee
(HiSIM Research Center, Hiroshima University, Higashi-Hiroshima 739-8530, Japan)
,
Maiti Tapas Kumar
(HiSIM Research Center, Hiroshima University, Higashi-Hiroshima 739-8530, Japan)
,
Ma Chenyue
(HiSIM Research Center, Hiroshima University, Higashi-Hiroshima 739-8530, Japan)
,
Miura-Mattausch Mitiko
(HiSIM Research Center, Hiroshima University, Higashi-Hiroshima 739-8530, Japan)
,
Miremadi Seyed-Ghassem
(Department of Computer Engineering, Sharif University of Technology, Tehran, Iran)
,
Mattausch Hans Jurgen
(HiSIM Research Center, Hiroshima University, Higashi-Hiroshima 739-8530, Japan)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
SISPAD
ページ:
97-100
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)