文献
J-GLOBAL ID:201702270340239757
整理番号:17A0312285
多重スルーシリコンビアを用いた3Dネットワークオンチップの設計方法論と諸性能と製作計量評価【Powered by NICT】
A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias
著者 (5件):
Said Mostafa
(Department of Electrical Engineering, Faculty of Engineering, Assiut University, Assiut, Egypt)
,
Shalaby Ahmed
(Department of Electronics and Communications, Egypt-Japan University of Science and Technology (E-JUST), Alexandria, Egypt)
,
Mehdipour Farhad
(E-JUST Center, Graduate School of Information Science and Electrical Engineering, Kyushu University, Fukuoka, Japan)
,
Biglari-Abhari Morteza
(Department of Electrical & Computer Engineering, University of Auckland, Auckland, New Zealand)
,
El-Sayed Mohamed
(Department of Electronics and Communications, Egypt-Japan University of Science and Technology (E-JUST), Alexandria, Egypt)
資料名:
Microprocessors and Microsystems
(Microprocessors and Microsystems)
巻:
43
ページ:
26-46
発行年:
2016年06月
JST資料番号:
H0781A
ISSN:
0141-9331
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
オランダ (NLD)
言語:
英語 (EN)