文献
J-GLOBAL ID:201702270955590945
整理番号:17A1062972
分数次数カオスシステムのFPGA実装【Powered by NICT】
FPGA implementation of fractional-order chaotic systems
著者 (5件):
Shah Divya K.
(Department of Electronics Engineering, Ramrao Adik Institute of Technology, Nerul, Navi Mumbai 400706, India)
,
Chaurasiya Rohit B.
(Department of Electronics Engineering, Ramrao Adik Institute of Technology, Nerul, Navi Mumbai 400706, India)
,
Vyawahare Vishwesh A.
(Department of Electronics Engineering, Ramrao Adik Institute of Technology, Nerul, Navi Mumbai 400706, India)
,
Pichhode Khushboo
(Department of Electronics Engineering, Ramrao Adik Institute of Technology, Nerul, Navi Mumbai 400706, India)
,
Patil Mukesh D.
(Department of Electronics and Telecommunication Engineering, Ramrao Adik Institute of Technology, Nerul, Navi Mumbai, India)
資料名:
AEUe
(AEUe)
巻:
78
ページ:
245-257
発行年:
2017年
JST資料番号:
A0447A
ISSN:
1434-8411
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
ドイツ (DEU)
言語:
英語 (EN)