文献
J-GLOBAL ID:201702271724600413
整理番号:17A0309494
BiNoCアーキテクチャを意識したタスク割当と通信スケジューリング方式【Powered by NICT】
A BiNoC architecture-aware task allocation and communication scheduling scheme
著者 (5件):
Tsai Wen-Chung
(Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung 413, Taiwan, ROC)
,
Chen Wei-De
(MediaTek Inc., Hsinchu 300, Taiwan, ROC)
,
Lan Ying-Cherng
(Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, ROC)
,
Hu Yu-Hen
(Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI 53706-1691, USA)
,
Chen Sao-Jie
(Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, ROC)
資料名:
Microprocessors and Microsystems
(Microprocessors and Microsystems)
巻:
42
ページ:
215-226
発行年:
2016年05月
JST資料番号:
H0781A
ISSN:
0141-9331
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
オランダ (NLD)
言語:
英語 (EN)