文献
J-GLOBAL ID:201702278982464541
整理番号:17A0151803
バイアス空間におけるCMOS FET劣化のマッピング: DRAM周辺デバイスへの応用
Mapping of CMOS FET degradation in bias space-Application to dram peripheral devices
著者 (12件):
Kaczer B.
(imec, Kapeldreef 75, Leuven B-3001, Belgium)
,
Franco J.
(imec, Kapeldreef 75, Leuven B-3001, Belgium)
,
Tyaginov S.
(TU Vienna, Gusshausstrasse 27-29, Vienna A-1040, Austria and Ioffe Institute, Saint-Petersburg 194021, Russia)
,
Jech M.
(TU Vienna, Gusshausstrasse 27-29, Vienna A-1040, Austria)
,
Rzepa G.
(TU Vienna, Gusshausstrasse 27-29, Vienna A-1040, Austria)
,
Grasser T.
(TU Vienna, Gusshausstrasse 27-29, Vienna A-1040, Austria)
,
O’Sullivan B. J.
(imec, Kapeldreef 75, Leuven B-3001, Belgium)
,
Ritzenhaler R.
(imec, Kapeldreef 75, Leuven B-3001, Belgium)
,
Schram T.
(imec, Kapeldreef 75, Leuven B-3001, Belgium)
,
Spessot A.
(imec, Kapeldreef 75, Leuven B-3001, Belgium)
,
Linten D.
(imec, Kapeldreef 75, Leuven B-3001, Belgium)
,
Horiguchi N.
(imec, Kapeldreef 75, Leuven B-3001, Belgium)
資料名:
Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena
(Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena)
巻:
35
号:
1
ページ:
01A109-01A109-6
発行年:
2017年01月
JST資料番号:
E0974A
ISSN:
2166-2746
CODEN:
JVTBD9
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)