文献
J-GLOBAL ID:201702284671791206
整理番号:17A0048554
65nm CMOSテクノロジのスタックフリー遅延ロックループと半ビット遅延ラインを備えた0.36 pJ/bit,0.025 mm2 12.5 Gbpsフォワードクロックレシーバ
A 0.36 pJ/bit, 0.025 mm${}^{¥text{2}}$, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology
著者 (6件):
Bae Woorham
(Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea)
,
Jeong Gyu-Seob
(Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea)
,
Park Kwanseo
(Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea)
,
Cho Sung-Yong
(Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea)
,
Kim Yoonsoo
(AnaPass, Seoul, South Korea)
,
Jeong Deog-Kyoon
(Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea)
資料名:
IEEE Transactions on Circuits and Systems 1: Regular Papers
(IEEE Transactions on Circuits and Systems 1: Regular Papers)
巻:
63
号:
9
ページ:
1393-1403
発行年:
2016年
JST資料番号:
C0226B
ISSN:
1549-8328
CODEN:
ITCSCH
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)