文献
J-GLOBAL ID:201702286195885569
整理番号:17A0328668
機能単位間の相互接続割当と高レベル合成におけるレジスタ【Powered by NICT】
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis
著者 (4件):
Hao Cong
(Graduate School of Information, Production and System, Kitakyushu, Japan)
,
Ni Jianmo
(School of Shanghai Jiao Tong University, Shanghai, China)
,
Wang Nan
(School of Information Science and Engineering, East China University of Science and Technology, Shanghai, China)
,
Yoshimura Takeshi
(Graduate School of Information, Production and System, Kitakyushu, Japan)
資料名:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
巻:
25
号:
3
ページ:
1140-1153
発行年:
2017年
JST資料番号:
W0516A
ISSN:
1063-8210
CODEN:
ITCOB4
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)