文献
J-GLOBAL ID:201702290855840039
整理番号:17A1273452
高アスペクト比高電圧デバイス面積効率を改善するための誘電体壁としての金型エッジ周辺の深いトレンチ終端(HARDT~2)法【Powered by NICT】
High aspect ratio deep trench termination (HARDT2) technique surrounding die edge as dielectric wall to improve high voltage device area efficiency
著者 (6件):
Yamaguchi Takuya
(Advanced Discrete Development Center, Discrete Semiconductor Division, Storage & Electronic Devices Solutions Company, Toshiba Corporation, Nomi, Ishikawa, Japan)
,
Okumura Hideki
(Advanced Discrete Development Center, Discrete Semiconductor Division, Storage & Electronic Devices Solutions Company, Toshiba Corporation, Nomi, Ishikawa, Japan)
,
Shiraishi Tatsuya
(Advanced Discrete Development Center, Discrete Semiconductor Division, Storage & Electronic Devices Solutions Company, Toshiba Corporation, Nomi, Ishikawa, Japan)
,
Fujita Tsuyoshi
(Advanced Discrete Development Center, Discrete Semiconductor Division, Storage & Electronic Devices Solutions Company, Toshiba Corporation, Nomi, Ishikawa, Japan)
,
Ata Yoshifumi
(Advanced Discrete Development Center, Discrete Semiconductor Division, Storage & Electronic Devices Solutions Company, Toshiba Corporation, Nomi, Ishikawa, Japan)
,
Kobayashi Kenya
(Advanced Discrete Development Center, Discrete Semiconductor Division, Storage & Electronic Devices Solutions Company, Toshiba Corporation, Nomi, Ishikawa, Japan)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
ISPSD
ページ:
479-482
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)