文献
J-GLOBAL ID:201802228510447629
整理番号:18A1895858
H.264の逆整数変換アルゴリズムの高速FPGAベース実装【JST・京大機械翻訳】
A High-Speed FPGA-based Implementation of Inverse Integer Transform Algorithm of H.264
著者 (6件):
Mukherjee Rohan
(Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India)
,
Poddar Arnab
(Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India)
,
Banerjee Anupam
(Advanced Technology Development Centre, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India)
,
Chakrabarti Indrajit
(Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India)
,
Dutta Pranab Kumar
(Department of Electrical Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India)
,
Ray Ajoy Kumar
(Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
INDICON
ページ:
1-6
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)