文献
J-GLOBAL ID:201802228879930212
整理番号:18A2163423
CDACコンパイラと合成可能アナログビルディングブロックを用いた再利用可能な符号ベースSAR ADC設計【JST・京大機械翻訳】
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks
著者 (6件):
Seo Min-Jae
(Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon)
,
Roh Yi-Ju
(Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon)
,
Chang Dong-Jin
(Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon)
,
Kim Wan
(Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon)
,
Kim Ye-Dam
(Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon)
,
Ryu Seung-Tak
(Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon)
資料名:
IEEE Transactions on Circuits and Systems 2: Express Briefs
(IEEE Transactions on Circuits and Systems 2: Express Briefs)
巻:
65
号:
12
ページ:
1904-1908
発行年:
2018年
JST資料番号:
W0347A
ISSN:
1549-7747
CODEN:
ITCSFK
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)