文献
J-GLOBAL ID:201802234885725014
整理番号:18A0516823
STT MRAMベースLLCsのための適応3T 3MTJメモリセルの設計【Powered by NICT】
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs
著者 (9件):
Xue Linuo
(Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA)
,
Wu Bi
(School of Electronic and Information Engineering, Beihang University, Beijing, China)
,
Zhang Beibei
(School of Electronic and Information Engineering, Beihang University, Beijing, China)
,
Cheng Yuanqing
(School of Electronic and Information Engineering, Beihang University, Beijing, China)
,
Wang Peiyuan
(Qualcomm Inc., San Diego, CA, USA)
,
Park Chando
(Qualcomm Inc., San Diego, CA, USA)
,
Kan Jimmy
(Qualcomm Inc., San Diego, CA, USA)
,
Kang Seung H.
(Qualcomm Inc., San Diego, CA, USA)
,
Xie Yuan
(Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA)
資料名:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
巻:
26
号:
3
ページ:
484-495
発行年:
2018年
JST資料番号:
W0516A
ISSN:
1063-8210
CODEN:
ITCOB4
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)