文献
J-GLOBAL ID:201802235603372838
整理番号:18A1303300
二項級数に基づく単一クロック平方根アルゴリズムとそのFPGA実装【JST・京大機械翻訳】
Single clock square root algorithm based on binomial series and its FPGA implementation
著者 (7件):
Bagala Tomas
(Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia)
,
Fibich Adam
(Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia)
,
Hagara Miroslav
(Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia)
,
Kubinec Peter
(Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia)
,
Ondracek Oldrich
(Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia)
,
Stofanik Vladimir
(Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia)
,
Stojanovic Radovan
(Faculty of Electrical Engineering, University of Montenegro, Podgorica, Montenegro)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2018
号:
MECO
ページ:
1-4
発行年:
2018年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)