文献
J-GLOBAL ID:201802240310987811
整理番号:18A0265850
二重ゲート(DG)p n i n TFETのドレイン電流モデル:運転の反転領域への蓄積【Powered by NICT】
Drain Current Model for Double Gate (DG) p-n-i-n TFET: Accumulation to Inversion Region of Operation
著者 (4件):
Upasana
(Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110021, India)
,
Narang Rakhi
(Department of Electronics, Sri Venkateswara College, University of Delhi, New Delhi 110021, India)
,
Saxena Manoj
(Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi 110078, India)
,
Gupta Mridula
(Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110021, India)
資料名:
Superlattices and Microstructures
(Superlattices and Microstructures)
巻:
104
ページ:
78-92
発行年:
2017年
JST資料番号:
D0600B
ISSN:
0749-6036
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
オランダ (NLD)
言語:
英語 (EN)