文献
J-GLOBAL ID:201802242883176791
整理番号:18A0942077
Crat GPUのための協調レジスタ割当とスレッドレベル並列性最適化の可能化【JST・京大機械翻訳】
CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs
著者 (7件):
Xie Xiaolong
(Center for Energy-efficient Computing and Applications, School of EECS, Peking University, Beijing, China)
,
Liang Yun
(Center for Energy-efficient Computing and Applications, School of EECS, Peking University, Beijing, China)
,
Li Xiuhong
(Center for Energy-efficient Computing and Applications, School of EECS, Peking University, Beijing, China)
,
Wu Yudong
(Center for Energy-efficient Computing and Applications, School of EECS, Peking University, Beijing, China)
,
Sun Guangyu
(Center for Energy-efficient Computing and Applications, School of EECS, Peking University, Beijing, China)
,
Wang Tao
(Center for Energy-efficient Computing and Applications, School of EECS, Peking University, Beijing, China)
,
Fan Dongrui
(Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China)
資料名:
IEEE Transactions on Computers
(IEEE Transactions on Computers)
巻:
67
号:
6
ページ:
890-897
発行年:
2018年
JST資料番号:
C0233A
ISSN:
0018-9340
CODEN:
ICTOB4
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)