文献
J-GLOBAL ID:201802260240864841
整理番号:18A0195538
CMOSコンパチブル製造プロセスを用いたTaN薄膜抵抗器の開発と特性化【Powered by NICT】
Development and characterization of TaN thin film resistor with CMOS compatible fabrication process
著者 (12件):
Kang Xiaoxu
(Process Technology Department, Shanghai IC R&D Center, Shanghai, 201210, China)
,
Zhu Limin
(PIE Department III, Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201206, China)
,
Zhu Xingwang
(PIE Department III, Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201206, China)
,
Zuo Qingyun
(Process Technology Department, Shanghai IC R&D Center, Shanghai, 201210, China)
,
Zhong Xiaolan
(Process Technology Department, Shanghai IC R&D Center, Shanghai, 201210, China)
,
Chen Shoumian
(Process Technology Department, Shanghai IC R&D Center, Shanghai, 201210, China)
,
Zhao Yuhang
(Process Technology Department, Shanghai IC R&D Center, Shanghai, 201210, China)
,
Liu Shanshan
(PIE Department III, Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201206, China)
,
Lu Hanwei
(PIE Department III, Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201206, China)
,
Wang Jianmin
(PIE Department III, Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201206, China)
,
Wang Wei
(PIE Department III, Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201206, China)
,
Zhang Bo
(PIE Department III, Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 201206, China)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
ASICON
ページ:
160-162
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)