文献
J-GLOBAL ID:201802262786641539
整理番号:18A1130451
FPGAプラットフォームのための高性能,資源効率,再構成可能な並列パイプライン化FFTプロセッサ【JST・京大機械翻訳】
A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms
著者 (4件):
Nguyen Ngoc Hung
(School of Electrical, Electronics and Computer Engineering, University of Ulsan, Bldg. #7, 93 Daehak-ro, Nam-gu, Ulsan 680-749, South Korea)
,
Khan Sheraz Ali
(School of Electrical, Electronics and Computer Engineering, University of Ulsan, Bldg. #7, 93 Daehak-ro, Nam-gu, Ulsan 680-749, South Korea)
,
Kim Cheol-Hong
(School of Electronics and Computer Engineering, Chonnam National University, Gwangju 500-757, South Korea)
,
Kim Jong-Myon
(School of Electrical, Electronics and Computer Engineering, University of Ulsan, Bldg. #7, 93 Daehak-ro, Nam-gu, Ulsan 680-749, South Korea)
資料名:
Microprocessors and Microsystems
(Microprocessors and Microsystems)
巻:
60
ページ:
96-106
発行年:
2018年
JST資料番号:
H0781A
ISSN:
0141-9331
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
オランダ (NLD)
言語:
英語 (EN)