文献
J-GLOBAL ID:201802268050824853
整理番号:18A1480535
電力増幅器のDPD線形化のためのハードウェア効率の良いフィードバック多項式トポロジー:理論とFPGA検証【JST・京大機械翻訳】
A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation
著者 (3件):
Cheang Chak-Fong
(Department of Electrical and Computer Engineering, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China)
,
Mak Pui-In
(Department of Electrical and Computer Engineering, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China)
,
Martins Rui P.
(Department of Electrical and Computer Engineering, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China)
資料名:
IEEE Transactions on Circuits and Systems 1: Regular Papers
(IEEE Transactions on Circuits and Systems 1: Regular Papers)
巻:
65
号:
9
ページ:
2889-2902
発行年:
2018年
JST資料番号:
C0226B
ISSN:
1549-8328
CODEN:
ITCSCH
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)