文献
J-GLOBAL ID:201802282437290502
整理番号:18A0200960
産業計測技術の検証による挿入損特性化のためのPCB設計と解析最適化【Powered by NICT】
PCB design and analysis optimization for insertion loss characterization by validating industry metrologies
著者 (6件):
Lin Cucumber
(Chung Yuan Christian University, Department of Electronic Engineering, 200 Chung Pei Road, Chung Li District, Taoyuan City, Taiwan (R.O.C.) 32023)
,
Shiue G. H.
(Chung Yuan Christian University, Department of Electronic Engineering, 200 Chung Pei Road, Chung Li District, Taoyuan City, Taiwan (R.O.C.) 32023)
,
Hsu Jimmy
(Intel Microelectronics Asia LLC, Taiwan Branch 20F, #369, Sec. 7, Zhong-Xiao E. Rd., Nan-Gang District, Taipei, Taiwan (R.O.C.) 11561)
,
Su Thonas
(Intel Microelectronics Asia LLC, Taiwan Branch 20F, #369, Sec. 7, Zhong-Xiao E. Rd., Nan-Gang District, Taipei, Taiwan (R.O.C.) 11561)
,
Lin Jay
(Intel Microelectronics Asia LLC, Taiwan Branch 20F, #369, Sec. 7, Zhong-Xiao E. Rd., Nan-Gang District, Taipei, Taiwan (R.O.C.) 11561)
,
Lai Cloud
(Intel Microelectronics Asia LLC, Taiwan Branch 20F, #369, Sec. 7, Zhong-Xiao E. Rd., Nan-Gang District, Taipei, Taiwan (R.O.C.) 11561)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
IMPACT
ページ:
327-330
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)