文献
J-GLOBAL ID:201802282468174071
整理番号:18A0185768
復号化垂直-水平共通部分表現除去アルゴリズムCSDに基づく計算効率の良い再構成可能な定数乗算アーキテクチャ【Powered by NICT】
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm
著者 (3件):
Hatai Indranil
(Electronics and Electrical Communication Engineering Department, IIT Kharagpur, Kharagpur, India)
,
Chakrabarti Indrajit
(Electronics and Electrical Communication Engineering Department, IIT Kharagpur, Kharagpur, India)
,
Banerjee Swapna
(Electronics and Electrical Communication Engineering Department, IIT Kharagpur, Kharagpur, India)
資料名:
IEEE Transactions on Circuits and Systems 1: Regular Papers
(IEEE Transactions on Circuits and Systems 1: Regular Papers)
巻:
65
号:
1
ページ:
130-140
発行年:
2018年
JST資料番号:
C0226B
ISSN:
1549-8328
CODEN:
ITCSCH
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)