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J-GLOBAL ID：201802283302876795 整理番号：18A0446832

活性ゲートとコバルト局所相互接続上の接触10nm高性能および低電力CMOS技術を特徴とする3~rd発生FinFETトランジスタ,自己整合4パターン形成【Powered by NICT】

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

著者 (56件)：

Auth C.

(Logic Technology Development)

,

Aliyarukunju A.

(Logic Technology Development)

,

Asoro M.

(Logic Technology Development)

,

Bergstrom D.

(Logic Technology Development)

,

Bhagwat V.

(Logic Technology Development)

,

Birdsall J.

(Logic Technology Development)

,

Bisnik N.

(Logic Technology Development)

,

Buehler M.

(Logic Technology Development)

,

Chikarmane V.

(Logic Technology Development)

,

Ding G.

(Logic Technology Development)

,

Fu Q.

(Logic Technology Development)

,

Gomez H.

(Logic Technology Development)

,

Han W.

(Logic Technology Development)

,

Hanken D.

(Logic Technology Development)

,

Haran M.

(Logic Technology Development)

,

Hattendorf M.

(Logic Technology Development)

,

Heussner R.

(Logic Technology Development)

,

Hiramatsu H.

(Logic Technology Development)

,

Ho B.

(Logic Technology Development)

,

Jaloviar S.

(Logic Technology Development)

,

Jin I.

(Logic Technology Development)

,

Joshi S.

(Logic Technology Development)

,

Kirby S.

(Logic Technology Development)

,

Kosaraju S.

(Logic Technology Development)

,

Kothari H.

(Logic Technology Development)

,

Leatherman G.

(Quality and Reliability Engineering, Intel Corporation)

,

Lee K.

(Logic Technology Development)

,

Leib J.

(Logic Technology Development)

,

Madhavan A.

(Logic Technology Development)

,

Marla K.

(Logic Technology Development)

,

Meyer H.

(Logic Technology Development)

,

Mule T.

(Logic Technology Development)

,

Parker C.

(Logic Technology Development)

,

Parthasarathy S.

(Logic Technology Development)

,

Pelto C.

(Logic Technology Development)

,

Pipes L.

(Logic Technology Development)

,

Post I.

(Logic Technology Development)

,

Prince M.

(Logic Technology Development)

,

Rahman A.

(Quality and Reliability Engineering, Intel Corporation)

,

Rajamani S.

(Logic Technology Development)

,

Saha A.

(Logic Technology Development)

,

Santos J. Dacuna

(Quality and Reliability Engineering, Intel Corporation)

,

Sharma M.

(Logic Technology Development)

,

Sharma V.

(Logic Technology Development)

,

Shin J.

(Logic Technology Development)

,

Sinha P.

(Logic Technology Development)

,

Smith P.

(Logic Technology Development)

,

Sprinkle M.

(Logic Technology Development)

,

Amour A. St.

(Logic Technology Development)

,

Staus C.

(Logic Technology Development)

,

Suri R.

(Logic Technology Development)

,

Towner D.

(Logic Technology Development)

,

Tripathi A.

(Logic Technology Development)

,

Tura A.

(Logic Technology Development)

,

Ward C.

(Logic Technology Development)

,

Yeoh A.

(Logic Technology Development)

資料名：

IEEE Conference Proceedings (IEEE Conference Proceedings)

巻： 2017 号： IEDM ページ： 29.1.1-29.1.4 発行年： 2017年
JST資料番号： W2441A 資料種別：会議録 (C)
記事区分：原著論文発行国：アメリカ合衆国 (USA) 言語：英語 (EN)

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