文献
J-GLOBAL ID:201802288668205939
整理番号:18A1770288
PLANARONOC:光ネットワークオンチップ*のための交差最小化を考慮した同時配置と経路選定【JST・京大機械翻訳】
PlanarONoC: Concurrent Placement and Routing Considering Crossing Minimization for Optical Networks-on-Chip*
著者 (6件):
Chuang Yu-Kai
(Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, 106, Taiwan)
,
Chen Kuan-Jung
(Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, 106, Taiwan)
,
Lin Kun-Lin
(Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, 106, Taiwan)
,
Fang Shao-Yun
(Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, 106, Taiwan)
,
Li Bing
(Chair of Electronic Design Automation, Technical University of Munich, Germany)
,
Schlichtmann Ulf
(Chair of Electronic Design Automation, Technical University of Munich, Germany)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2018
号:
DAC
ページ:
1-6
発行年:
2018年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)