文献
J-GLOBAL ID:201902228701966419
整理番号:19A2718407
サージ応力下のデバイスの故障を調べるための共設計回路シミュレーション【JST・京大機械翻訳】
Co-design Circuit Simulation to Investigate the Failure of Devices under Surge Stress
著者 (4件):
Wang Yize
(Key Laboratory of Microelectronics Device and Circuit (MoE), Institute of Microelectronic, Peking University,,,Beijing,,China,100871)
,
Wang Yuan
(Key Laboratory of Microelectronics Device and Circuit (MoE), Institute of Microelectronic, Peking University,,,Beijing,,China,100871)
,
Li Yunhao
(Key Laboratory of Microelectronics Device and Circuit (MoE), Institute of Microelectronic, Peking University,,,Beijing,,China,100871)
,
Huang Ru
(Key Laboratory of Microelectronics Device and Circuit (MoE), Institute of Microelectronic, Peking University,,,Beijing,,China,100871)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2019
号:
EMC Sapporo/APEMC
ページ:
262-265
発行年:
2019年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)