文献
J-GLOBAL ID:201902268096269901
整理番号:19A2115769
MVMのための効率的なマルチビット誤り耐性設計【JST・京大機械翻訳】
Efficient Multi-Bit Error Tolerant design for MVM
著者 (4件):
Hitesh P G
(Department of Electronics and Communication Engineering, Amrita School of Engineering, Bengaluru, India)
,
Venkatesh Pasam
(Department of Electronics and Communication Engineering, Amrita School of Engineering, Bengaluru, India)
,
Thirumal Reddy P Sai
(Department of Electronics and Communication Engineering, Amrita School of Engineering, Bengaluru, India)
,
Vinodhini M.
(Department of Electronics and Communication Engineering, Amrita School of Engineering, Bengaluru, India)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2019
号:
ICECA
ページ:
24-28
発行年:
2019年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)