文献
J-GLOBAL ID:201902272922846305
整理番号:19A2423659
Vedic数学を用いた高次浮動小数点乗算器の低電力で面積効率の良い設計【JST・京大機械翻訳】
Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics
著者 (4件):
Loganathan Haripriya
(Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India)
,
Rohit Patnaikuni
(Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India)
,
Suneel Polamarasetty Sai
(Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India)
,
Balasubramanian Karthi
(Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India)
資料名:
Lecture Notes in Electrical Engineering
(Lecture Notes in Electrical Engineering)
巻:
569
ページ:
475-486
発行年:
2020年
JST資料番号:
W5070A
ISSN:
1876-1100
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
ドイツ (DEU)
言語:
英語 (EN)