文献
J-GLOBAL ID:202002223313643843
整理番号:20A1072641
SERAD:束化データプロトコルを用いたソフトエラー耐性非同期設計【JST・京大機械翻訳】
SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol
著者 (5件):
Aketi Sai Aparna
(Department of Electrical Engineering, Indian Institute of Technology Gandhinagar (IITGN), Gandhinagar, India)
,
Gupta Smriti
(Department of Electrical Engineering, Indian Institute of Technology Gandhinagar (IITGN), Gandhinagar, India)
,
Cheng Huimei
(Ming Hsieh Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USA)
,
Mekie Joycee
(Department of Electrical Engineering, Indian Institute of Technology Gandhinagar (IITGN), Gandhinagar, India)
,
Beerel Peter A.
(Ming Hsieh Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USA)
資料名:
IEEE Transactions on Circuits and Systems 1: Regular Papers
(IEEE Transactions on Circuits and Systems 1: Regular Papers)
巻:
67
号:
5
ページ:
1667-1677
発行年:
2020年
JST資料番号:
C0226B
ISSN:
1549-8328
CODEN:
ITCSCH
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)