文献
J-GLOBAL ID:202002224956339607
整理番号:20A0861540
180nm技術を用いた低電圧フローティングゲートMOSFETベース電流ミラー回路の実現【JST・京大機械翻訳】
Implementation of Low Voltage Floating Gate MOSFET based Current Mirror Circuits using 180nm technology
著者 (4件):
Mishra Ansuman
(Manipal Institute of Technology, Manipal Academy of Higher Education,Department of Electronics and Communication Engineering,Manipal,India.)
,
Bhat M Vineeth
(Manipal Institute of Technology, Manipal Academy of Higher Education,Department of Electronics and Communication Engineering,Manipal,India.)
,
Pai Prasad Krishna
(Manipal Institute of Technology, Manipal Academy of Higher Education,Department of Electronics and Communication Engineering,Manipal,India.)
,
Kamath D V
(Manipal Institute of Technology, Manipal Academy of Higher Education,Department of Electronics and Communication Engineering,Manipal,India.)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2019
号:
ICISC
ページ:
268-272
発行年:
2019年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)