文献
J-GLOBAL ID:202002232760653325
整理番号:20A0910339
タイル型RRAMアーキテクチャに基づく深い神経回路網加速器【JST・京大機械翻訳】
A Deep Neural Network Accelerator Based on Tiled RRAM Architecture
著者 (5件):
Wang Qiwen
(University of Michigan,Department of Electrical Engineering and Computer Science,Ann Arbor,Michigan,USA,48109)
,
Wang Xinxin
(University of Michigan,Department of Electrical Engineering and Computer Science,Ann Arbor,Michigan,USA,48109)
,
Lee Seung Hwan
(University of Michigan,Department of Electrical Engineering and Computer Science,Ann Arbor,Michigan,USA,48109)
,
Meng Fan-Hsuan
(University of Michigan,Department of Electrical Engineering and Computer Science,Ann Arbor,Michigan,USA,48109)
,
Lu Wei D.
(University of Michigan,Department of Electrical Engineering and Computer Science,Ann Arbor,Michigan,USA,48109)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2019
号:
IEDM
ページ:
14.4.1-14.4.4
発行年:
2019年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)