文献
J-GLOBAL ID:202002232764800275
整理番号:20A0819353
180nm CMOSにおけるPAM4送信機のための適切な補償回路設計【JST・京大機械翻訳】
Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS
著者 (5件):
Ichii Yudai
(The University of Shiga Prefecture,Department of Electronic Systems Engineering,2500 Hassaka, Hikone, Shiga,Japan,522-8533)
,
Noguchi Ryosuke
(The University of Shiga Prefecture,Department of Electronic Systems Engineering,2500 Hassaka, Hikone, Shiga,Japan,522-8533)
,
Inoue Toshiyuki
(The University of Shiga Prefecture,Department of Electronic Systems Engineering,2500 Hassaka, Hikone, Shiga,Japan,522-8533)
,
Tsuchiya Akira
(The University of Shiga Prefecture,Department of Electronic Systems Engineering,2500 Hassaka, Hikone, Shiga,Japan,522-8533)
,
Kishine Keiji
(The University of Shiga Prefecture,Department of Electronic Systems Engineering,2500 Hassaka, Hikone, Shiga,Japan,522-8533)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2019
号:
ISOCC
ページ:
210-211
発行年:
2019年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)