文献
J-GLOBAL ID:202002240436309990
整理番号:20A0819338
人工神経回路網のエネルギー効率的処理のためのビット精度再構成可能なディジタル・インメモリコンピューティング・マクロ【JST・京大機械翻訳】
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks
著者 (5件):
Kim Hyunjoon
(School of Electrical and Electronic Engineering, Nanyang Technological University Singapore,50 Nanyang Avenue,Singapore,639798)
,
Chen Qian
(School of Electrical and Electronic Engineering, Nanyang Technological University Singapore,50 Nanyang Avenue,Singapore,639798)
,
Yoo Taegeun
(School of Electrical and Electronic Engineering, Nanyang Technological University Singapore,50 Nanyang Avenue,Singapore,639798)
,
Kim Tony Tae-Hyoung
(School of Electrical and Electronic Engineering, Nanyang Technological University Singapore,50 Nanyang Avenue,Singapore,639798)
,
Kim Bongjin
(School of Electrical and Electronic Engineering, Nanyang Technological University Singapore,50 Nanyang Avenue,Singapore,639798)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2019
号:
ISOCC
ページ:
166-167
発行年:
2019年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)