文献
J-GLOBAL ID:202002272628245198
整理番号:20A0373746
RRAMによる神経形態チップのためのFPGAベースのハードウェアエミュレータ【JST・京大機械翻訳】
An FPGA-Based Hardware Emulator for Neuromorphic Chip With RRAM
著者 (7件):
Luo Tao
(Institute of High Performance Computing, Agency for Science, Technology and Research, Singapore)
,
Wang Xuan
(Institute of High Performance Computing, Agency for Science, Technology and Research, Singapore)
,
Qu Chuping
(Institute of High Performance Computing, Agency for Science, Technology and Research, Singapore)
,
Lee Matthew Kay Fei
(Institute of High Performance Computing, Agency for Science, Technology and Research, Singapore)
,
Tang Wai Teng
(Institute of High Performance Computing, Agency for Science, Technology and Research, Singapore)
,
Wong Weng-Fai
(School of Computing, National University of Singapore, Singapore)
,
Goh Rick Siow Mong
(Institute of High Performance Computing, Agency for Science, Technology and Research, Singapore)
資料名:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
(IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)
巻:
39
号:
2
ページ:
438-450
発行年:
2020年
JST資料番号:
B0142C
ISSN:
0278-0070
CODEN:
ITCSDI
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)