文献
J-GLOBAL ID:202002272915885800
整理番号:20A1956338
65nm CMOSにおけるスパイク時間依存塑性によるメモリベースオンチップ学習【JST・京大機械翻訳】
Processing-In-Memory-Based On-Chip Learning With Spike-Time-Dependent Plasticity in 65-nm CMOS
著者 (5件):
Kim Daehyun
(School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA)
,
She Xueyuan
(School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA)
,
Rahman Nael Mizanur
(School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA)
,
Chekuri Venkata Chaitanya Krishna
(School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA)
,
Mukhopadhyay Saibal
(School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA)
資料名:
IEEE Solid-State Circuits Letters
(IEEE Solid-State Circuits Letters)
巻:
3
ページ:
278-281
発行年:
2020年
JST資料番号:
W3688A
ISSN:
2573-9603
CODEN:
ISCLCN
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)