文献
J-GLOBAL ID:202102275232207714
整理番号:21A0151633
3nmゲートオールアラウンドナノシートFETのための設計技術の同時最適化【JST・京大機械翻訳】
Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs
著者 (7件):
Wang Meng
(Key Laboratory of Multidimensional Information Processing, East China Normal University,Department of Electrical Engineering,Shanghai,China,200241)
,
Sun Yabin
(Key Laboratory of Multidimensional Information Processing, East China Normal University,Department of Electrical Engineering,Shanghai,China,200241)
,
Li Xiaojin
(Key Laboratory of Multidimensional Information Processing, East China Normal University,Department of Electrical Engineering,Shanghai,China,200241)
,
Shi Yanling
(Key Laboratory of Multidimensional Information Processing, East China Normal University,Department of Electrical Engineering,Shanghai,China,200241)
,
Hu Shaojian
(Integrated Circuit Research and Development Center,Shanghai,China,201210)
,
Shang Enming
(Integrated Circuit Research and Development Center,Shanghai,China,201210)
,
Chen Shoumian
(Integrated Circuit Research and Development Center,Shanghai,China,201210)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2020
号:
ICSICT
ページ:
1-3
発行年:
2020年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)