文献
J-GLOBAL ID:202102276521025710
整理番号:21A1812210
セルピッチ低減と内部抵抗最適化による1.2kV級SBD埋め込みSiC MOSFETの比オン抵抗と短絡抵抗トレードオフの改善【JST・京大機械翻訳】
Improving the specific on-resistance and short-circuit ruggedness tradeoff of 1.2-kV-class SBD-embedded SiC MOSFETs through cell pitch reduction and internal resistance optimization
著者 (8件):
Kono Hiroshi
(Toshiba Electronic Devices & Storage Corporation,Japan)
,
Asaba Shunsuke
(Toshiba Electronic Devices & Storage Corporation,Japan)
,
Ohashi Teruyuki
(Toshiba Corporation,Corporate Research & Development Center,Kawasaki,Japan)
,
Ogata Takahiro
(Toshiba Electronic Devices & Storage Corporation,Japan)
,
Furukawa Masaru
(Toshiba Electronic Devices & Storage Corporation,Japan)
,
Sano Kenya
(Toshiba Electronic Devices & Storage Corporation,Japan)
,
Yamaguchi Masakazu
(Toshiba Electronic Devices & Storage Corporation,Japan)
,
Suzuki Hisashi
(Toshiba Electronic Devices & Storage Corporation,Japan)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2021
号:
ISPSD
ページ:
227-230
発行年:
2021年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)