文献
J-GLOBAL ID:202202246905870048
整理番号:22A0977398
5nm技術ノード設計,最適化,性能評価におけるカーボンナノチューブSRAM 第1部:CNFETトランジスタの最適化【JST・京大機械翻訳】
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part I: CNFET Transistor Optimization
著者 (12件):
Chen Rongmei
(IMEC, Leuven, Belgium)
,
Chen Lin
(School of Microelectronics, Beihang University, Beijing, China)
,
Liang Jie
(School of Microelectronics, Shanghai University, Shanghai, China)
,
Cheng Yuanqing
(School of Microelectronics, Beihang University, Beijing, China)
,
Elloumi Souhir
(Microelectronics Department, LIRMM, CNRS, University of Montpellier, Montpellier, France)
,
Lee Jaehyun
(Synopsys, Ltd., Glasgow, U.K.)
,
Xu Kangwei
(School of Microelectronics, Beihang University, Beijing, China)
,
Georgiev Vihar P.
(School of Engineering, University of Glasgow, Glasgow, U.K.)
,
Ni Kai
(Department of Microsystems, Rochester Institute of Technology, Rochester, NY, USA)
,
Debacker Peter
(IMEC, Leuven, Belgium)
,
Asenov Asen
(School of Engineering, University of Glasgow, Glasgow, U.K.)
,
Todri-Sanial Aida
(Microelectronics Department, LIRMM, CNRS, University of Montpellier, Montpellier, France)
資料名:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
巻:
30
号:
4
ページ:
432-439
発行年:
2022年
JST資料番号:
W0516A
ISSN:
1063-8210
CODEN:
ITCOB4
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)