文献
J-GLOBAL ID:202202257013396309
整理番号:22A0630823
VCDLベースの開ループ時間領域比較器を有する12ビット20kS/s 640-nW SAR ADC【JST・京大機械翻訳】
A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator
著者 (6件):
Zhou Xiaochuan
(School of Electronics and Information Engineering and the School of Microelectronics, Xian Jiaotong University, Xi’an, China)
,
Gui Xiaoyan
(School of Electronics and Information Engineering and the School of Microelectronics, Xian Jiaotong University, Xi’an, China)
,
Gusev Marjan
(Faculty of Computer Science and Engineering, Ss. Cyril and Methodius University, Skopje, North Macedonia)
,
Ackovska Nevena
(Faculty of Computer Science and Engineering, Ss. Cyril and Methodius University, Skopje, North Macedonia)
,
Zhang Yanlong
(School of Electronics and Information Engineering and the School of Microelectronics, Xian Jiaotong University, Xi’an, China)
,
Geng Li
(School of Electronics and Information Engineering and the School of Microelectronics, Xian Jiaotong University, Xi’an, China)
資料名:
IEEE Transactions on Circuits and Systems 2: Express Briefs
(IEEE Transactions on Circuits and Systems 2: Express Briefs)
巻:
69
号:
2
ページ:
359-363
発行年:
2022年
JST資料番号:
W0347A
ISSN:
1549-7747
CODEN:
ITCSFK
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)