文献
J-GLOBAL ID:202202261094771308
整理番号:22A0630896
「位相リセット」スキームによる6.15±10.9Gb/s 0.58 pJ/ビット基準レスハーフレートクロックとデータ回復【JST・京大機械翻訳】
A 6.15-10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme
著者 (6件):
Xiao Wenbo
(School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China)
,
Huang Qiwei
(School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China)
,
Mosalam Hamed
(School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China)
,
Zhan Chenchang
(School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China)
,
Li Zhiqun
(Institute of RF- &OE-ICs, Southeast University, Nanjing, China)
,
Pan Quan
(School of Microelectronics, Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China)
資料名:
IEEE Transactions on Circuits and Systems 1: Regular Papers
(IEEE Transactions on Circuits and Systems 1: Regular Papers)
巻:
69
号:
2
ページ:
634-644
発行年:
2022年
JST資料番号:
C0226B
ISSN:
1549-8328
CODEN:
ITCSCH
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)