文献
J-GLOBAL ID:202202281122231600
整理番号:22A1175420
応答曲面法を用いたゲートオールアラウンド無接合トランジスタの最適化【JST・京大機械翻訳】
Optimization of Gate all-around Junctionless Transistor Using Response Surface Methodology
著者 (5件):
Ramesh R.
(Device Modeling Laboratory, School of Electrical and Electronics Engineering, SASTRA Deemed University, Thanjavur, India)
,
Pon Adhithan
(Device Modeling Laboratory, School of Electrical and Electronics Engineering, SASTRA Deemed University, Thanjavur, India)
,
Babu P. Dinesh
(School of Mechanical Engineering, SASTRA Deemed University, Thanjavur, India)
,
Carmel Santhia
(Device Modeling Laboratory, School of Electrical and Electronics Engineering, SASTRA Deemed University, Thanjavur, India)
,
Bhattacharyya Arkaprava
(Device Modeling Laboratory, School of Electrical and Electronics Engineering, SASTRA Deemed University, Thanjavur, India)
資料名:
Silicon
(Silicon)
巻:
14
号:
6
ページ:
2499-2508
発行年:
2022年
JST資料番号:
W4947A
ISSN:
1876-9918
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
ドイツ (DEU)
言語:
英語 (EN)