Yui Koyanagi, Tomoaki Ukezono, Toshinori Sato. A Light-Weight and Tamper-Resistant AES Implementation by FPGAs. The 2024 IEEE International Symposium on Circuits and Systems. 2024
Yui Koyanagi, Tomoaki Ukezono. Masking Regularity of Noise for Tamper-resistant Design on FPGAs. The 25th Workshop on Synthesis And System Integration of Mixed Information technologies. 2024. 46-49
Yui Koyanagi, Tomoaki Ukezono. A Cost-aware Generation Method of Disposable Random Value Exploiting Parallel S-box Implementation for Tamper-resistant AES Design. 14th International Workshop on Advances in Networking and Computing. 2023. 318-322
Tomoaki Ukezono, Yui Koyanagi. Reusing Outputs from S-boxes for Tamper Resistant Design. 3rd International Conference on Electrical, Computer and Energy Technologies. 2023. 1362-1367
Yui Koyanagi, Tomoaki Ukezono. A Cost-sensitive and Simple Masking Design for Side-channels. 2023 IEEE Region 10 Technical Conference. 2023. 731-736
2023/10 - The 10th International Conference on Electrical Engineering, Computer Science and Informatics Best Paper Award Improving Tamper-Resistance Exploiting Clock Phase Shifter Embedded in FPGAs
2023/09 - The 2023 IEEE Region 10 Symposium Best Paper Award Runner-Up A Countermeasure to Power Analysis Attack by Arbitrarily Injecting Multiple Types of Noise
2023/01 - 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023) Poster Award A Countermeasure to Power Analysis Attack in Flip Flops
2022/08 - The 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022) Best Paper Award An Accuracy-Controllable Approximate Adder for FPGAs