文献
J-GLOBAL ID:201702239715663837
整理番号:17A0274326
DLAU:FPGA上でのスケーラブルな深層学習加速器ユニット【Powered by NICT】
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
著者 (6件):
Wang Chao
(University of Science and Technology of China, Hefei, China)
,
Gong Lei
(University of Science and Technology of China, Hefei, China)
,
Yu Qi
(University of Science and Technology of China, Hefei, China)
,
Li Xi
(University of Science and Technology of China, Hefei, China)
,
Xie Yuan
(University of California at Santa Barbara, Santa Barbara, CA, USA)
,
Zhou Xuehai
(University of Science and Technology of China, Hefei, China)
資料名:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
(IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)
巻:
36
号:
3
ページ:
513-517
発行年:
2017年
JST資料番号:
B0142C
ISSN:
0278-0070
CODEN:
ITCSDI
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)