文献
J-GLOBAL ID:201802286315751964
整理番号:18A0446754
過渡TCADシミュレーションにより研究した負性静電容量FinFETの展望【Powered by NICT】
Perspective of negative capacitance FinFETs investigated by transient TCAD simulation
著者 (7件):
Ota Hiroyuki
(National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan)
,
Fukuda Koichi
(National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan)
,
Ikegami Tsutomu
(National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan)
,
Hattori Junichi
(National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan)
,
Asai Hidehiro
(National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan)
,
Migita Shinji
(National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan)
,
Toriumi Akira
(Graduate School of Engineering, The University of Tokyo, Tokyo, Japan)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
IEDM
ページ:
15.2.1-15.2.4
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)