文献
J-GLOBAL ID:202002215599084060
整理番号:20A0911287
64ビットRSFQセキュアコプロセッサのための8ビットビットスライス茶暗号加速器【JST・京大機械翻訳】
An 8-bit Bit-Slice TEA-Cryptographic Accelerator for 64-bit RSFQ Secure Coprocessors
著者 (6件):
Yu Pei-Shi
(University of Chinese Academy of Sciences,Beijing,China)
,
Tang Guang-Ming
(State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China)
,
Ye Xiao-Chun
(State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China)
,
Fan Dong-Rui
(State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China)
,
Zhang Zhi-Min
(State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China)
,
Sun Ning-Hui
(State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2019
号:
ISEC
ページ:
1-4
発行年:
2019年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)