文献
J-GLOBAL ID:202002284857718268
整理番号:20A0915408
整定時間改善方式を用いた11ビットリング増幅器パイプラインADC【JST・京大機械翻訳】
An 11-bit Ring Amplifier Pipeline ADC with Settling-Time Improvement Scheme
著者 (8件):
Bae Chankyu
(Cesign,Gyeonggi-do,Republic of Korea)
,
Shin Seungwoo
(University of Seoul,Dept. of Electrical and Computer Engineering,Seoul,Republic of Korea)
,
Jung Jiteck
(University of Seoul,Dept. of Electrical and Computer Engineering,Seoul,Republic of Korea)
,
Park Minsu
(University of Seoul,Dept. of Electrical and Computer Engineering,Seoul,Republic of Korea)
,
Kwon Kibaek
(University of Seoul,Dept. of Electrical and Computer Engineering,Seoul,Republic of Korea)
,
Kim Jinhyun
(University of Seoul,Dept. of Electrical and Computer Engineering,Seoul,Republic of Korea)
,
Jung Taekyoung
(University of Seoul,Dept. of Electrical and Computer Engineering,Seoul,Republic of Korea)
,
Choi Joongho
(University of Seoul,Dept. of Electrical and Computer Engineering,Seoul,Republic of Korea)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2020
号:
ICEIC
ページ:
1-4
発行年:
2020年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)