Rchr
J-GLOBAL ID:200901014310093172
Update date: Sep. 19, 2024
Takagi Kazuyoshi
タカギ カズヨシ | Takagi Kazuyoshi
Affiliation and department:
Job title:
Professor
Homepage URL (1):
http://www.arch.info.mie-u.ac.jp/
Research field (4):
Electronic devices and equipment
, Information networks
, Computer systems
, Information theory
Research keywords (6):
超伝導ディジタル回路
, 論理設計支援
, 論理回路設計
, Superconductive Digital Circuits
, Computer-Aided Logic Design
, Logic Circuit Design
Research theme for competitive and other funds (24):
- 2018 - 2021 Researches on Testing and Reliable Design of Superconducting Rapid Single-Flux-Quantum Circuits
- 2016 - 2020 Studies on hardware assist of floating point function calculation
- 2015 - 2018 Studies on Layout Design Methods for Logic Circuits using Superconducting Devices
- 2012 - 2015 studies on high-reliability timing design methods for logic circuits using advanced devices
- 2012 - 2015 Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation
- 2008 - 2010 Research on synthesis of easily-testable arithmetic circuits
- 2006 - 2009 Studies on Logic Design and Design Automation of Single-Flux-Quantum Circuits based on Localized Electromagnetic Waves
- 2005 - 2007 次世代集積回路設計のための決定グラフによる論理関数表現に関する研究
- 2004 - 2007 ハードウェアアルゴリズムの性能評価に関する研究
- 2002 - 2004 Researches on hardware algorithms for arithmetic operations in finite fields.
- 2002 - 超伝導デバイスのディジタル応用
- 2002 - Digital Applications of Superconductive Devices
- 2000 - 2001 種々の決定グラフを用いた論理関数表現とその回路合成への応用に関する研究
- 1999 - 2001 Implementation of Adaptable Hardware and Software for Changing Environment
- 1998 - 2000 Studies on hardware algorithms for high-performance arithmetic circuits
- 1997 - 1998 コンテンツに適応する発展的ソフトウェアの構成法
- 1997 - 1997 コンテンフに適応する発展的ソフトウェアの構成法
- 1995 - 1997 Research on Reconfigurable General Purpose Co-processor Systems and Their Optimized Hardware/Software Codesign Compiler
- 1995 - ディジタルLSI設計
- 1995 - Digital LSI Design
- 1993 - LSI CADのためのデータ構造とアルゴリズム
- 1993 - Data Structures and Algorithms for LSI CAD
- 1991 - 回路計算複雑さの理論
- 1991 - Circuit Complexity Theory
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Papers (102):
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Nobutaka Kito, Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi. Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits. IEEE Transactions on Applied Superconductivity. 2023. 33. 5. 1-5
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Masamitsu Tanaka, Ryo Sato, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi. Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency. Applied Physics Letters. 2023. 122. 19
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Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi. Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates. IEEE Transactions on Applied Superconductivity. 2022. 32. 5. 1-9
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Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi. Logic-Depth-Aware Technology Mapping Method for RSFQ Logic Circuits With Special RSFQ Gates. IEEE Transactions on Applied Superconductivity. 2022. 32. 4. 1-5
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Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao. Splitter-Aware Multiterminal Routing with Length-Matching Constraint for RSFQ Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2021. 40. 11. 2251-2264
more...
MISC (315):
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Supporting TOPPERS/ASP3 Kernel to mROS to Improve its Capability. Proceedings of Asia Pacific Conference on Robot IoT System Development and Platform. 2020. 2019. 31-32
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A functionality expansion of the lightweight runtime environment mROS for the user defined message types. Proceedings of Asia Pacific Conference on Robot IoT System Development and Platform. 2020. 2019. 1-7
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mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices. 2020. 61. 2
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鬼頭信貴, 高木一義. An RSFQ Variable-Precision Matrix Multiplier Utilizing Bit-Level Processing. 電子情報通信学会大会講演論文集(CD-ROM). 2020. 2020
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A functionality expansion of the lightweight runtime environment mROS for the user defined message types. 2019. 2019. 62-69
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Works (9):
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単一磁束量子回路による再構成可能な低電力高性能プロセッサ
2006 - 2011
-
テスト容易な演算回路の自動合成に関する研究
2008 - 2010
-
局在電磁波配線を用いた単一磁束量子論理回路の設計および設計支援に関する研究
2006 - 2009
-
次世代集積回路設計のための決定グラフによる論理関数表現に関する研究
2005 - 2007
-
ハードウェアアルゴリズムの性能評価に関する研究
2004 - 2007
more...
Education (6):
Professional career (2):
- Master of Engineering (Kyoto University)
- Doctor of Engineering (Kyoto University)
Work history (10):
- 2019/04 - 現在 Mie University Dept. Information Engineering, G.S. Information Engineering Professor
- 2011/04 - 2019/03 Kyoto University Dept. Communications and Computer Engineering, G.S. Informatics Associate Professor
- 2007/04 - 2018/03 The University of Tokyo VDEC Cooperative Researcher
- 2007/04 - 2011/03 Nagoya University Dept. Information Engineering, G.S. Information Science Associate Professor
- 2006/07 - 2007/03 Nagoya University Dept. Information Engineering, G.S. Information Science Associate Professor
- 2005/04 - 2007/03 The University of Tokyo VDEC Visiting Researcher
- 2003/04 - 2006/06 Nagoya University Dept. Information Engineering, G.S. Information Science Assistant Professor
- 2000/02 - 2003/03 Nagoya University Dept. Information Engineering, G.S. Engineering Assistant Professor
- 1999/04 - 2000/01 Nagoya University Dept. Information Engineering, G.S. Engineering Assistant Professor
- 1995/04 - 1999/03 Nara Institute of Science and Technology Research Associate
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Association Membership(s) (4):
LAシンポジウム
, 情報処理学会
, 電子情報通信学会
, IEEE
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