Rchr
J-GLOBAL ID：200901016318469026   Update date: Sep. 22, 2024

Sasao Tsutomu

Sasao Tsutomu
Affiliation and department：
Meiji University School of Science and Technology

About Meiji University School of Science and Technology


Job title： Visiting Professor
Research field  (1)： Computer systems
Research theme for competitive and other funds  (20)：
  • 2020 - 2023 Minimization of variables for classification functions, and its applications.
  • 2017 - 2020 インデックス生成関数の分解に関する研究
  • 2014 - 2018 High-speed pattern matching
  • 2011 - 2014 Logic synthesis using linear transformation and memories.
  • 2007 - 2009 A study on the realization and application of content-addressable memory using general-purpose memory
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Papers (227)：
  • Jon T. Butler, Tsutomu Sasao, Shinobu Nagayama. On the distribution of sensitivities of symmetric Boolean functions. CoRR. 2023. abs/2306.14401
  • Tsutomu Sasao, Anders Holmgren, Patrik Eklund. A Logical Method to Predict Outcomes After Coronary Artery Bypass Grafting. ISMVL. 2023. 202-208
  • Tsutomu Sasao. Data Mining Using Multi-Valued Logic Minimization. ISMVL. 2023. 105-110
  • Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler. Decomposition-Based Representation of Symmetric Multiple-Valued Functions. ISMVL. 2023. 76-81
  • Tsutomu Sasao. Easily Reconstructable Logic Functions. ISMVL. 2023. 12-17
ｍore...
MISC (45)：
  • I. Syafalni, T. Sasao, X. Wen. Bit-Flip Errors Detection using Random Partial Don't-Care Keys for a Soft-Error-Tolerant TCAM. Proceedings of the 27th International Workshop on Logic and Synthesis. 2018. 124-131
  • A Memory Based Realization of the Binarized Deep Convolutional Neural Network. 2016. 116. 210. 63-68
  • A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division. 2016. 115. 400. 227-232
  • A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division. 2016. 115. 398. 227-232
  • An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope. 2015. 115. 343. 39-44
ｍore...
Books (13)：
  • Index Generation Functions
    Morgan and Claypool 2019
  • Applications of zero-suppressed decision diagrams
    Morgan & Claypool 2015 ISBN:9781627056496
  • Applications of Zero-Suppressed Decision Diagrams
    2014
  • Memory-Based Logic Synthesis
    Springer(USA) 2011
  • Memory-based logic synthesis
    Springer 2011 ISBN:9781441981035
ｍore...
Lectures and oral presentations  (10)：
  • Cyclic row-shift decompositions for incompletely specified index generation functions
    (IWLS-2013 2013)
  • Forty years of logic synthesis: Memoir
    (RM-2013 2013)
  • Combinational computing: One object per clock
    (RM-2013 2013)
  • Hardware index to set partition converter
    (The 9th International Symposium on Applied Reconfigurable Computing (ARC2013) 2013)
  • An architecture for IPv6 lookup using parallel index generation units
    (The 9th International Symposium on Applied Reconfigurable Computing (ARC2013) 2013)
ｍore...
Professional career (1)：
  • Ph.D (Osaka University)
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