Research keywords (7):
Design for Testability
, Test Generation
, High Level Synthesis
, Asynchronous Circuits
, ストカスティックコンピューティング
, Dependable Computing
, Design and Test of Digital Systems
Research theme for competitive and other funds (3):
Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue. Effective utilization of register-transfer paths based on enhancing multiplexer functions in RTL scan design. Digest of Papers 19th IEEE Workshop on RTL and High Level Testing (WRTLT '18). 2018. 1-6
Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue. Experimental evaluation of test cost reduction by scan chain testing in RTL scan circuits. Digest of Papers 18th IEEE Workshop on RTL and High Level Testing (WRTLT '17). 2017. 1-6