KAZUO TAKI

タキカズオ | KAZUO TAKI

Affiliation and department：
Job title： Professor

Research field (2)： Electronic devices and equipment , Information theory

Research keywords (5)： Natural Language Recognition , Artificial Intelligence , Integrated Circuit Design , Computer Architecture LSI Design Methodology , Computer Architecture

Papers (51)：

Masao Morimoto, Makoto Nagata, Kazuo Taki. Asymmetric slope dual mode differential logic circuit for compatibility of low-power and high-speed operations. IEICE TRANSACTIONS ON ELECTRONICS. 2007. E90C. 4. 675-682
Y Fukumizu, S Ohno, M Nagata, K Taki. Communication scheme for a highly collision-resistive RFID system. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. 2006. E89A. 2. 408-415
M Morimoto, Y Tanaka, M Nagata, K Taki. Logic synthesis technique for high speed differential dynamic logic with asymmetric slope transition. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. 2005. E88A. 12. 3324-3331
M Morimoto, M Nagata, K Taki. High-speed digital circuit design using differential logic with asymmetric signal transition. IEICE TRANSACTIONS ON ELECTRONICS. 2005. E88C. 10. 2001-2008
M Nagata, T Okumoto, K Taki. A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits. IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2005. 40. 4. 813-819

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MISC (48)：

S. Haruna, N. Sanada, H. Kinoh, K. Sumiya, K. Taki. A GUI software design model and its runtime architecture for digital AV applications. Proceedings - International Symposium on Multimedia Software Engineering. 2000. 347-351. 347-351
Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Yeol Lee, Hiroyuki Ochi, Kazao Taki, Takao Tsuda. A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2000. 33-34
Low Power Pass-Transistor Logic and Application Examples. Trans. Inst. Electronics, Information and Communication Engineers - [J80-A/5,753-764]. 1997
An Application of Temperature Parallel Simulated Annealing to the Traveling Salesman Problem and Its Experimental Analysis. Trans. Inst. Electronics, Information and Communication Engineers - [J80-D-I/2,127-136]. 1997
An Application of Temperature Parallel Simulated Annealing to the Traveling Salesman Problem and Its Efficient Implementation on the Distributed Memory Parallel Mechine. Parallel Processing Simposium JSPP'96 - [/,153]. 1996

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Education (4)：

- 1979 Kobe University Graduate School of Engineering
- 1979 Kobe University Graduate School, Division of Engineering
- 1976 Kobe University Faculty of Engineering
- 1976 Kobe University Faculty of Engineering

Professional career (2)：

Doctor of Engineering (Kobe University)
Master of Engineering (Kobe University)

Work history (7)：

2016 - 現在 Kobe University Graduate School of Science, Technology and Innovation
2012 - 2016 Kobe University Center for Collaborative Research and Technology Development (CREATE)
2002 - 2012 AIL Co. Ltd.
1992 - 2005 Kobe University Faculty of Engineering Department of Computer and Systems Engineering
1982 - 1992 (財)新世代コンピュータ技術開発機構(ICOT) 研究所研究員・室長

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Awards (2)：

2000 - 平成12年度情報処理学会山下記念研究所賞 (プラスチック・ハード・マクロ技術による低消費電力算術演算器)
1986 - 昭和62年度元岡賞(LISPマシン, PSI / マルチPSIの開発)

Association Membership(s) (3)：

IEEE , 電子情報通信学会 , 情報処理学会

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