Takeuchi Yoshinori

Affiliation and department：
Job title： Associate Professor

Research field (4)： Computer systems , High-performance computing , Control and systems engineering , Communication and network engineering

Research keywords (7)： Computer Architecture , Embedded Systems , SoC Design , Design Automation , VLSI Design Methodology , VLSI Design , Signal Processing

Research theme for competitive and other funds (23)：

2020 - 2024 網膜と視覚野の情報処理と通信に学んだ脳刺激型人工視覚の開発
2017 - 2020 Study for Low Energy Information Sensing for IoT Devices
2016 - 2019 Hardware-oriented Algorithms and Implementation Methodology for Object Recognition
2014 - 2017 Higher Reliable Task Assignment Method for Embedded Multiprocessor
2013 - 2016 Research for Task assignment methods considering input data variability

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Papers (260)：

Naoya Tanaka, Shogo Hirayama, Yoshinori Takeuchi. CODEC system using EG2C chips and power control with a sleep mode for a visual prosthesis. The 25th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2024). 2024. 335-340
Ryota Hattori, Yoshinori Takeuchi. Multiple regression analysis considering multicollinearity for;estimating CPU;cycles using performance counters. The 25th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2024). 2024. 101-106
中井智哉, 武内良典. カスタム命令追加設計支援環境を用いた自然対数演算のためのRISC-V プロセッサの設計. DAシンポジウム2024論文集. 2024. 2024. 128-133
平山聖冴, 田中尚哉, 武内良典. 人工視覚システムのための圧縮伸張チップEG2Cの消費電力評価. 電子情報通信学会信学技報. 2023. 123. VLD2023-78. 249-254
有山響, 武内良典. CUDAを用いたグローバルメモリアクセスの削減によるSpiking Neural Networkシミュレーションの高速化. 情報処理学会研究報告, SLDM-203. 2023. 10. 1-2

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MISC (485)：

中井智哉, 吉澤翔悟, 武内良典. RISC-Vのカスタム命令を用いた自然対数演算. 2024年電子情報通信学会総合大会. 2024. A-6-01
有山響, 武内良典. SNNシミュレーションにおけるCUDA生成フレームワークGeNNのGPUスレッド数の実行時間への影響. 024年電子情報通信学会総合大会. 2024. D-2-07
Proposal of a Bedtime ECG Measurement System for Detecting Heart Diseases. 2016. 115. 518. 217-222
TAKEUCHI YOSHINORI, YU JAEHOON, YAMANAKA TATSUYA, Khan Arif Ullah, SEKINE MASAKI, IMAI MASAHARU. Proposal of an Unconscious Bioelectric Potential Measurement System for Bedtime ECG Acquisition. IEICE technical report. Computer systems. 2015. 114. 506. 291-296
TAKEUCHI YOSHINORI, YU JAEHOON, YAMANAKA TATSUYA, Khan Arif Ullah, SEKINE MASAKI, IMAI MASAHARU. Proposal of an Unconscious Bioelectric Potential Measurement System for Bedtime ECG Acquisition. IEICE technical report. Dependable computing. 2015. 114. 507. 291-296

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Patents (11)：

電気信号取得装置
電気信号取得装置
勾配方向ヒストグラム生成装置及び勾配方向ヒストグラム生成方法
生体情報の圧縮方法およびデータ圧縮装置
電子トリアージシステム

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Books (7)：

論理回路
オーム社 2016 ISBN:9784274218064
"ASIP Meister,"Processor Description Languages,Prabhat Mishra and Nikil Dutt, eds.
Springer 2008
"Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model,"VLSI-SoC: Research Trends in VLSI and Systems on Chip,Giovanni De Micheli, Salvador Mir, Ricardo Reis, eds,
Springer 2007
System Level Synthesis
Kluwer Academic Publishers 1999
'Compiler Generation Techniques for Embedded Processors and thier Application to HW/SW Codesign' System Level Synthesis, (共著)
1999

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Lectures and oral presentations (2)：

Challenges for Processor Instruction Extension in MPSoC Era
(19th International Forum on MPSoC for Software-defined Hardware 2019 (MPSoC 2019) 2019)
Coding Analysis for Spiking Neural Network Models
(18th International Forum on MPSoC for Software-defined Hardware 2018 2018)

Works (13)：

Optimization for Dynamic Reconfigurable Components
2008 -
災害時救命救急支援を目指した人間情報センシングシステムの開発
2008 -
医療用汎用SoCデバイスの開発
2008 -
マルチプロセッサSoCのアーキテクチャ設計最適化手法
2008 -
ダイナミック・リコンフィギャラブル・コンポーネントの設計最適化手法
2008 -

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Education (4)：

- 1992 Tokyo Institute of Technology Graduate School, Division of Science and Engineering
- 1992 Tokyo Institute of Technology Science of Engineering
- 1987 Tokyo Institute of Technology Faculty of Engineering
- 1987 Tokyo Institute of Technology School of Engineering

Professional career (2)：

(BLANK) (Tokyo Institute of Technology)
(BLANK) (Tokyo Institute of Technology)

Work history (9)：

2018 - 現在 Kindai University Faculty of Science and Engineering
2007 - 2017 Osaka University Graduate School of Information Science and Technology
2002 - 2006 Osaka University Graduate School of Information Science and Technology
1999 - 2002 : 大阪大学大学院基礎工学研究科助教授
1997 - 1999 : 大阪大学大学院基礎工学研究科講師

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Committee career (16)：

2024/04 - 現在電気学会関西支部協議員
2023/06 - 現在 IPSJ Transactions on System LSI Design Methodology Associate Editors-in-Chief
2023/01 - 現在電子情報通信学会『Special Section on VLSI Design and CAD Algorithms』編集委員会編集委員
2014 - 現在情報処理学会「組込みシステム工学」特集号編集委員会編集委員
2022/11 - 2023/06 電子情報通信学会『Special Section on Circuits and Systems』編集委員会編集委員

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Awards (8)：

2019 - IPSJ IPSJ Transactions on System LSI Design Methodology, Best Paper Award Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA
2016 - 情報処理学会組込みシステム研究会優秀論文賞共有資源モデル記述を用いた実時間制御システムのモデリング手法
2011 - The Institute of Electronics Engineers of Korea The IEEK Semiconductor & Device Society paper award
2010 - IEEE Solid-State Circuits Society Japan Chapter Academic Research Award
2010 - IEEE Solid-State Circuits Society Japan Chapter IEEE Solid-State Circuits Society Japan Chapter Academic 0Research Award

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Association Membership(s) (5)：

電気学会 , ACM , INFORMATION PROCESSING SOCIETY OF JAPAN , IEEE , THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS

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