Osana Yasunori

オサナヤスノリ | Osana Yasunori

Affiliation and department：
Job title： Associate Professor
Homepage URL (1)： http://kuma.osana-lab.org/

Research field (2)： Computer systems , High-performance computing

Research theme for competitive and other funds (5)：

2020 - 2024 Development and Deployment of Continuous Data Acquisition System Realizing ALICE GEM-TPC
2019 - 2022 CPUとFPGAによる高性能ヘテロジニアス並列分散計算フレームワークの開発
2016 - 2019 CPU-FPGA混在クラスタによるCFD向け高性能計算システムの研究
2013 - 2015 Development of elemental technology of reconfigurable LSI based computer systems for CFD acceleration
2009 - 2011 Acceleration techniques for practical CFD packages using FPGAs

Papers (65)：

Yuiki Tani, Yasunori Osana. A 100Gbps-ready Low Latency on-Chip Router for FPGA clusters. IEEE 42nd International Conference on Consumer Electronics. 2024. 1-3
Yasunori Osana, Satoshi Fujii. An SDR implementation of HF ocean radar on FPGA SoC. IEEE 42nd International Conference on Consumer Electronics. 2024. 1-3
松田暁, 山田寛喜, 藤井智史, 長名保範, 宇野亨. A Study on Improving Aircraft Target Detection Performance Using Range and Doppler Walk Correction in Ocean Radar. 電子情報通信学会論文誌 B(Web). 2023. J106-B. 11
小泉達寛, 山田寛喜, 藤井智史, 長名保範, 宇野亨. Experimental Study on Ocean, Ships and Airplanes Observation for Polarimetric Ocean Radar. 電子情報通信学会論文誌 B(Web). 2022. J105-B. 7
Shun Kasai, Yasunori Osana. A driver-based approach for DMA transfer between FPGA-GPU. 2022 Tenth International Symposium on Computing and Networking(CANDARW). 2022. 103-108

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MISC (37)：

坂本洋平, 長名保範. ストリーム計算による拡散方程式の実装と性能評価 (リコンフィギャラブルシステム). 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2017. 117. 221. 13-18
FPGA Design Contest : To Advocate FPGA and Its Design Method. 2017. 100. 2. 109-112
坂本洋平, 松田紘作, 大久保慎也, 長名保範. 部分再構成によるCPU-FPGA混在クラスタの実現へむけた研究 (リコンフィギャラブルシステム). 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2016. 116. 210. 51-56
Introduction to 2015 FPGA Trax contest. 2015. 115. 109. 109-112
KYAN Katsuki, ARAKAKI Makoto, HIRAI Yusuke, NAKASONE Hiroki, FUJITA Naoyuki, AMANO Hideharu, OSANA Yasunori. Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D. Technical report of IEICE. VLD. 2015. 114. 426. 139-143

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Books (1)：

Lectures and oral presentations (79)：

Kyokkoへの仮想チャネル機能の実装
(電子情報通信学会技術研究報告(Web) 2023)
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA)
(電子情報通信学会技術研究報告(Web) 2023)
RISC-Vソフトコアプロセッサと教育用マイコンシステムの試作
(電子情報通信学会技術研究報告(Web) 2023)
Evaluation of Vector Register Sharing Mechanism by Simulation
(情報処理学会研究報告(Web) 2023)
Kyokkoの通信レイテンシ性能評価
(電子情報通信学会技術研究報告(Web) 2023)

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Professional career (1)：

Work history (4)：

2023/04 - Kumamoto University Associate Professor
2011/05 - 2023/03 University of the Ryukyus Faculty of Engineering
2008/09 - 2011/04 Seikei University Faculty of Science and Technology, Department of Computer and Information Science
2006/04 - 2008/09 Keio University Faculty of Science and Technology, Department of Biosciences and Infomatics

Committee career (1)：

2010/11 - 2015/05 IEICE Editorial Committee of IEICE Transactions on Information and Systems

Awards (1)：

Association Membership(s) (3)：

IEEE Computer Society , 日本ゲノム微生物学会 , 電子情報通信学会

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